The present invention relates generally to methods and systems employed in the manufacture of electrical circuits and more particularly to the use of direct laser imaging for forming solder bumps on integrated circuit substrates.
A known method for connecting integrated circuits to printed circuit board employs so-called xe2x80x9cflip-chipxe2x80x9d technology. An electrical circuit is formed on one side of an integrated circuit substrate, and solder bump contacts are formed on a layer overlaying the electrical circuit. The integrated circuit substrate is placed face down onto an interconnect, such as a multi-chip module or BGA substrate, so that the solder bump contacts are in registered contact with an array of contacts, such as surface mount pads, formed on the interconnect. The substrate and printed circuit board are heated to melt the solder and establish electrical connect between the integrated circuit and the interconnect.
The following U.S. Patents are considered relevant to the art of solder bump preparation: U.S. Pat. No. 5,024,372 to Altman et al; U.S. Pat. No. 5,118,027 to Braun et al.; U.S. Pat. No. 5,161,257 to Yung; U.S. Pat. No. 5,293,006 to Yung; U.S. Pat. No. 5,323,947 to Juskey et al.; U.S. Pat. No. 5,447,264 to Koopman et al.; U.S. Pat. No. 5,539,153 to Schwiebert; U.S. Pat. No. 5,672,542 to Schwiebert; U.S. Pat. No. 5,738,269 to Masterton; U.S. Pat. No. 5,829,668 to George et al.; U.S. Pat. No. 5,938,106 to Pierson; U.S. Pat. No. 6,053,397 to Kaminski; U.S. Pat. No. 6,053,398 to Iizuka et al.; U.S. Pat. No. 6,056,191 to Brouillette et al.; U.S. Pat. No. 6,085,968 to Swindlehurst et al.; U.S. Pat. No. 6,109,507 to Yagi et al.
The present invention seeks to provide improved apparatus and methods for forming high density solder bumps on semiconductor substrates.
There is thus provided in accordance with a preferred embodiment of the present invention a method for forming bumps on an integrated circuit comprising employing a scanning direct laser imager to selectably expose a photosensitive layer deposited on an integrated circuit substrate thereby to define regions overlying selected portions of the integrated circuit substrate; developing the photosensitive layer thereby to selectively remove the photosensitive layer at the regions; and applying a solder composition to the predetermined regions, thereby to define solder bumps overlying the selected portions of the integrated circuit substrate.
Preferably the photosensitive layer is a solder mask.
Preferably the exposed regions have a spatial density which exceeds a spatial density which is realizable using an exposure mask.
Alternatively and additionally the exposed regions of photoresist preferably produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which is realizable using an exposure mask.
Moreover, in accordance with a preferred embodiment of the invention the employing a scanning laser direct imager, developing the photosensitive layer, and applying a solder composition take place waferwise prior to dicing of the integrated circuit substrate into individual dies.
Preferably, the electrical circuit is an integrated circuit and the substrate comprises a semiconductor substrate.
Additionally, in accordance with a preferred embodiment of the invention metal bases, providing an underbump metalization, are formed to overlay selected portions of the integrated circuit substrate, and the regions exposed in the photosensitive layer overly the bases.
Preferably the metal bases are formed by depositing a metal layer on the substrate; coating the metal layer with a photoresist; selectively exposing the photoresist to define a multiplicity of locations on the photoresist; developing the exposed photoresist and removing the photoresist other than at predetermined locations, thereby to expose the metal layer other than at the predetermined locations; and etching the metal layer to remove the metal layer other than at the predetermined locations to define a multiplicity of metal bases formed on the substrate.
Preferably, the substrate and the metal bases thereon are both coated with a layer of photosensitive solder mask used in the format on of solder bumps.
There is thus provided in accordance with a preferred embodiment of the present invention a system for forming bumps on an integrated circuit comprising a scanning laser direct imager selectably exposing a photosensitive layer deposited on an integrated circuit substrate thereby to define regions in the photosensitive layer overlying selected portions of the integrated circuit substrate; a developer developing the photosensitive layer to selectively remove the photosensitive layer at the defined regions; and a solder applicator applying a solder composition to the defined regions, thereby to define bumps overlying the selected portions of the integrated circuit substrate.
Preferably the photosensitive layer is a solder mask.
Preferably the direct laser imager defines exposed regions having a spatial density which exceeds a spatial density which is realizable using an exposure mask.
Alternatively and additionally the direct laser imager preferably defines exposed regions of the photosensitive layer to produce apertures having walls whose perpendicularity to a surface of the integrated circuit substrate exceeds the perpendicularity which is realizable using an exposure mask.
Preferably the developer and the solder applicator operate waferwise prior to doing of the integrated circuit substrate into individual dies.
Preferably the electrical circuit comprises an integrated circuit and the substrate comprises a semiconductor substrate.
In accordance with a preferred embodiment of the invention, the system for forming bumps on an integrated circuit substrate includes: a laser emitting laser light; a modulator receiving the laser light and modulating the laser light in accordance with control data received from a controller; and a polygonal mirror receiving the modulated laser and scanning the modulated laser light to expose the photoresist in a predetermined pattern.
Preferably the system further includes a metal base applier applying metal bases overlying selected portions of the integrated circuit substrate and wherein the regions overly the bases.
Preferably the metal base applier includes: a metal layer depositer depositing a metal layer on the substrate; a photoresist coater coating the metal layer with a photoresist; a laser direct imaging system selectively exposing the photoresist to define a multiplicity of locations; a developer developing the exposed photoresist and removing the photoresist other than at the locations, thereby to expose the metal layer other than at the locations; and an etcher removing the metal layer other than at the locations to define a multiplicity of metal bases formed on the substrate.
Preferably the system further includes a photosensitive layer coater coating the substrate and the metal bases thereon with a layer of photosensitive solder mask.
In accordance with a preferred embodiment of the invention, the system includes a laser emitting laser light; a modulator receiving the laser light and modulating the laser light in accordance with control data received from a controller; and a polygonal mirror receiving the modulated laser and scanning the modulated laser light to expose the photoresist in a predetermined pattern.
There is thus provided in accordance with a preferred embodiment of the invention a method for forming bumps on an integrated circuit, comprising: exposing a first photosensitive layer deposited on an integrated circuit substrate thereby to define regions in the photosensitive layer overlying selected portions of the integrated circuit substrate; applying a second photosensitive coating to the integrated circuit substrate; employing a scanning laser direct imaging system to expose the second photosensitive coating to define apertures in the second photosensitive coating generally overlying the portions; processing the second photosensitive coating to form apertures therein; and applying a solder composition to the apertures to form bumps. Preferably the bumps overly the selected portions of the integrated circuit.
There is thus provided in accordance with another preferred embodiment of the present invention a method for forming a portion of an electrical circuit on an integrated circuit substrate comprising: loading a first integrated circuit substrate and at least a second integrated circuit substrate onto a laser pattern exposure system; and exposing a selected portion of a photosensitive layer deposited on the second integrated circuit substrate prior to completing an exposure sequence exposing part of an electrical circuit pattern to be formed on a photosensitive layer deposited on the first integrated circuit substrate.
There is thus provided in accordance with still another preferred embodiment of the present invention a method for forming a portion of an electrical circuit on an integrated circuit substrate comprising: loading an integrated circuit substrate onto a laser pattern exposure system, wherein the substrate has formed on a surface thereof at least part of an integrated circuit pattern and a fiducial pattern having a known geometry with reference to the integrated circuit pattern, and the substrate is at least partially coated with a photosensitive coating; ascertaining the location of the fiducial pattern; adjusting digital data representing a portion of an electrical circuit to be formed on the integrated circuit substrate according the location of the fiducial pattern; and exposing a selected portion of the photosensitive layer with a laser beam according to a pattern supplied by the adjusted digital data.